As the integration and performance of semiconductor devices advance, analysis of defects of the semiconductor devices is increasingly becoming difficult. In response, to facilitate the analysis of defects of semiconductor devices as much as possible, various techniques for analyzing defects of semiconductor devices have been developed. According to one method for analyzing defects of semiconductor devices, an electron beam inspection apparatus is used to acquire a voltage contrast image and identify defect positions.
According to this method, first, a semiconductor device is polished by polishing or the like, so that a surface of a conductive layer (wirings or vias) to be observed is exposed. Next, the surface of the semiconductor device is charged to a desired voltage, and the exposed conductive layer is next irradiated with charged particles by an electronic beam. Secondary electrons are released from the semiconductor device, and a voltage contrast image formed thereby is observed by a scanning electron microscope (SEM). If a disconnection defect or a short-circuit defect is present in a lower layer of the conductive layer to be observed, the obtained voltage contrast image is different from that obtained from a normal semiconductor device. Thus, by acquiring voltage contrast images of defective and good semiconductor devices and comparing the images with each other, inconsistent positions are detected.
For example, Patent Document 1 discloses an automatic inspection system for an x-ray mask and the like. According to this document, by irradiating a conductive substrate with charged particles by an electron beam, detecting any of the generated secondary electrons, reflection electrons, and transmission electrons, and comparing an image formed by the detected signals with an image used as a reference, defects are automatically detected.
In addition, Patent Document 2 proposes a failure analysis apparatus as an improvement of a conventional technique. According to Patent Document 2, defects are analyzed by using an absorption electric potential method. Based on this method, first, a surface of a wiring or via to be observed is exposed by polishing, and the exposed surface is irradiated with charged particles by an electron beam. Whether a current leaks from the wiring to be analyzed to a substrate of a semiconductor integrated circuit device is displayed as a voltage contrast image. The voltage contrast image obtained by the absorption electric potential method is compared with an expectation image generated by pattern design data. When an end point of the wiring to be analyzed is a layer connected to a drain region of a metal oxide semiconductor (MOS) transistor, a low contrast is obtained by the absorption electric potential method. On the other hand, when the end point is a layer connected to a gate electrode of a MOS transistor, a high contrast is obtained (paragraphs 0015, 0026, and 0027 of Patent Document 2). When an end point of the wiring to be analyzed is a drain region of a MOS transistor, if a disconnection defect is present in the wiring, a high contrast is obtained. In this way, a disconnection defect can be detected (paragraphs 0032 to 0044 of Patent Document 2). When an end point of the wiring to be analyzed is a gate electrode of a MOS transistor, if a short-circuit defect is present in the wiring and the short-circuit defect causes a leakage current path between the wiring and a semiconductor substrate, a low contrast is obtained. In this way, a short-circuit defect can be detected (paragraphs 0045 to 0047 of Patent Document 2). Thus, Patent Document 2 uses the voltage contrast image obtained by the absorption electric potential method and the expectation image generated by design data, to detect the presence of a current leakage. Namely, defects are detected based on binary data (high contrast or low contrast).
Patent Document 1: Japanese Patent Kokai Publication No. JP-A-5-258703, which corresponds to U.S. Pat. No. 5,502,306.
Patent Document 2: Japanese Patent Kokai Publication No. JP2007-155449A